Capacitor in semiconductor device and manufacturing method

ABSTRACT

The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an upper electrode formed over the dielectric layer.

The present application claims priority under 35 U.S.C. 119 and 35U.S.C. 365 to Korean Patent Application No. 10-2005-0134350 (filed onDec. 29, 2005), which is hereby incorporated by reference in itsentirety.

BACKGROUND

With the increasingly large scale of integration of semiconductordevices, the space for forming capacitors is decreasing. Therefore,intense research efforts have been directed toward assuring sufficientcapacitance in the space available.

The capacitance of a capacitor is determined by the area of theelectrodes, the dielectric constant of a dielectric layer, and thedistance between electrodes. Accordingly, in order to increase thecapacitance, methods of increasing the effective area of a capacitor, ofdecreasing the thickness of a dielectric layer between two electrodes,and of replacing the dielectric layer with a material having a highdielectric constant have been intensively and extensively studied.

The method of increasing the effective area takes chip real estate awayfrom other devices, due to the high degree of integration andminiaturization. A better solution is to increase the capacitancethrough optimizing the layering process. However, it becomes difficultto deposit the upper film and the structure becomes complicated, therebyresulting in a difficult manufacturing process. Further, when thedielectric constant is increased or the thickness of the dielectriclayer is decreased, leakage current may be increased and faulty devicesmay result from electrical breakdown or the like.

SUMMARY

Embodiments relate to a capacitor in a semiconductor device and amanufacturing method thereof, and more particularly, to a capacitorhaving a structure of metal/insulator/metal (MIM) and a manufacturingmethod thereof.

Embodiments relate to a capacitor with greater capacitance and whichavoids the production of faulty devices.

Embodiments relate to a capacitor in a semiconductor device, comprisinga substrate, a lower electrode formed over the substrate, a diffusionbarrier formed over the lower electrode, a plurality of agglomeratesformed over the diffusion barrier, a dielectric layer formed along thesurface of the agglomerates to thus form an uneven surface, and an upperelectrode formed over the dielectric layer.

The agglomerates may comprise a low-melting-point metal, and thelow-melting-point metal may be Sn or Zn.

The dielectric layer may comprise at least one selected from amongSi₃N₄, SiO₂, Ta₂O₅, TiO₂, PZT, PLZT, and BaTiO₃.

The diffusion barrier may comprise Ru or RuO₂.

The agglomerates may have a spherical shape, and the projected area ofall of the agglomerates may constitute 50˜60% of the area of thediffusion barrier.

Embodiments relate to a method of manufacturing a capacitor in asemiconductor device, comprising forming a first metal film over asubstrate, forming a second metal film over the first metal film,forming a low-melting-point metal film over the second metal film,thermally treating the low-melting-point metal film to form sphericalagglomerates, forming a dielectric film over the agglomerates, forming athird metal film over the dielectric film, and etching the third metalfilm, the dielectric film, the agglomerates, an oxide film, and thefirst metal film.

The second metal film may be formed of Ru.

After forming the second metal film, the method may further compriseoxidizing the second metal film, and such oxidizing may be performed bythermally treating the second metal film at 300˜400° C. in an atmosphereof N₂O or O₂ gas.

The low-melting-point metal film may be formed of Zn or Sn.

The low-melting-point metal film may be formed through atomic layerdeposition or the like.

The thermal treating may be performed at a temperature equal to or lessthan 200° C. in an inert gas atmosphere.

As such, the inert gas may comprise at least one selected from among Ar,He, Ne, Kr, Xe, and Rn.

The dielectric film may be formed in a thickness of about 100 Å.

BRIEF DESCRIPTION OF THE DRAWINGS

Example FIG. 1 illustrates a cross sectional view of a capacitor in asemiconductor device, according to embodiments; and

Example FIGS. 2 to 4 sequentially illustrate cross sectional views ofthe process of manufacturing a semiconductor device, according toembodiments.

DETAILED DESCRIPTION

In the drawings, thicknesses are exaggerated in order to clearly depictthe plurality of layers and regions, wherein like parts appearing in thedrawings are represented by like reference numerals.

FIG. 1 illustrates a cross sectional view of the structure of acapacitor in a semiconductor device, according to embodiments.

As illustrated in FIG. 1, a capacitor 114 is composed of a lowerelectrode 102, a diffusion barrier 104, agglomerates 106, a dielectriclayer 108, and an upper electrode 110.

Specifically, as illustrated in the drawing, the lower electrode 102 isformed over the substrate 100.

The substrate includes semiconductor elements (not shown) and/or metalwires, or the like, which may be electrically connected to thesemiconductor elements. The lower electrode 102 is also electricallyconnected to the semiconductor elements and/or metal elements on thesubstrate. The lower electrode 102 may be formed of a single layerconsisting of W, Al or Ti, or of multiple layers or sublayers consistingof TiN or TaN.

The diffusion barrier 104 is formed over the lower electrode 102, and aplurality of agglomerates 106 are formed over the diffusion barrier 104.

The diffusion barrier 104 functions to prevent the diffusion of metalatoms located above the diffusion barrier 104 to the lower film, or ofmetal atoms located under the diffusion barrier 104 to the upper film.Such a diffusion barrier 104 is formed of Ru or RuO₂ in a thickness of10˜1,000.

The agglomerates 106 may be formed in a spherical shape to increase thesurface area of the film over the agglomerates 106. A low-melting-pointmetal, such as Zn or Ru is aggregated to form agglomerates 106. Further,the agglomerates 106 may or may not be uniformly distributed over thediffusion barrier 104. The projected area of all of the agglomerates 106constitutes 40˜60% of the area of the diffusion barrier 104.

The dielectric layer 108 and the upper electrode 110 are layered on theagglomerates 106. Since the agglomerates are spherical, the surface areaof dielectric layer 108 formed over the surface of the agglomerates isincreased. Moreover, the dielectric layer 108 has an uneven surface dueto the agglomerates 106, and the average thickness thereof may be, forexample, about 100 Å.

The dielectric layer 108 may be formed of a single layer or a doublelayer consisting of at least one of Si₃N₄, SiO₂, Ta₂O₅, TiO₂, PZT, PLZT,and BaTiO₃.

As in the lower electrode, the upper electrode 110 may be formed of asingle layer consisting of W, Al, Ti, or the like, or of multiple layersor sublayers consisting of TiN, TaN, or the like.

A barrier metal layer (not shown) may be further formed between theupper electrode 110 and the dielectric layer 108 in order to increasecontact properties and prevent the migration of metal atoms of the upperelectrode 110. The barrier metal layer may be formed of one or morelayers consisting of Ti or TiN.

In embodiments, it is easy to increase the surface area of thedielectric layer 108 using the agglomerates. Thereby, the capacitance ofthe capacitor may be readily increased without changing the design ofthe semiconductor device or the interlayer structure thereof.

An insulating layer, for example TEOS (tetra ethyl ortho silicate), isformed on the upper electrode 110 to cover the capacitor 114.

The method of manufacturing the capacitor in the semiconductor device isdescribed below, with reference to the appended drawings.

Example FIGS. 2 to 4 sequentially illustrate cross sectional views of anexample of a process of manufacturing the capacitor, according toembodiments.

As illustrated in FIG. 2, a first metal film and a second metal film arelayered over a substrate 100 through sputtering or the like. The firstmetal film 102 a may be formed of W, and the second metal film 104 a maybe formed of Ru.

Thereafter, the second metal film 104 a may be oxidized through thermaltreatment at 300˜400° C. in a plasma atmosphere of O₂ or N₂O, thusforming an oxide film 104 b composed of, for example, RuO₂.

As illustrated in example FIG. 3, a low-melting-point metal, for exampleSn, is deposited over the oxide film 104 b, thus forming alow-melting-point metal film. In this example, a layer of Sn 200 Å thickis formed through atomic layer deposition or the like.

Subsequently, the low-melting-point metal film is agglomerated to formspherical agglomerates 106. The low-melting-point metal film may beagglomerated, for example, through thermal treatment at a temperatureequal to or less than 200° C. in an inert gas atmosphere. The reason thefilm agglomerates is to decrease the surface energy of the thin film. Ifthe temperature is higher than 200° C., the thin film does notagglomerate, but evaporates.

As such, the inert gas includes at least one gas selected from among Ar,He, Ne, Kr, Ze, and Rn.

Further, a dielectric material is deposited over the agglomerates 106,thus forming a dielectric film 108 a. The dielectric film 108 a isformed with a thickness of about 100 Å along the surface of theagglomerates 106. Furthermore, since the dielectric film 108 a isunevenly formed, the surface area thereof is enlarged.

As illustrated in FIG. 4, a metal is deposited over the dielectric film108 a through sputtering or the like, thus forming a third metal film110 a. The third metal film 110 a may be composed of W.

Then, as illustrated in FIG. 1, the third conductive film 110 a, thedielectric film 108 a, the agglomerates 106, the oxide film 104 b, andthe first conductive film 102 a are etched through a selective etchingprocess, thereby completing a capacitor composed of the upper electrode110, the dielectric layer 108, the agglomerates 106, the diffusionbarrier 104 and the lower electrode 102.

Depending on the design of the capacitor, the lower electrode 102 may bewider than the upper electrode 110, or it may be the same width.

Thereafter, an oxide material, or the like, is deposited to cover thecapacitor 114, thus forming an interlayer insulating film 112. Theinterlayer insulating film may be formed with a thickness of 5000˜6000Å, for example. Moreover, processes of forming metal wires, metal lines,metal connections and/or an interlayer insulating film may be furtherconducted, if necessary.

As described hereinbefore, embodiments relate to a capacitor in asemiconductor device and a manufacturing method thereof. According toembodiments, spherical agglomerates are formed to increase the surfacearea of a dielectric layer, such that the capacitance of the capacitorcan be easily increased without changing the design of the semiconductordevice or the structure thereof, thereby providing a semiconductordevice having high quality.

It will be obvious and apparent to those skilled in the art that variousmodifications and variations can be made in the embodiments disclosed.Thus, it is intended that the disclosed embodiments cover the obviousand apparent modifications and variations, provided that they are withinthe scope of the appended claims and their equivalents.

1. A capacitor comprising: a substrate; a lower electrode formed overthe substrate; a diffusion barrier formed over the lower electrode; aplurality of agglomerates formed over the diffusion barrier; adielectric layer covering the agglomerates and having an uneven surfacedue to the agglomerates; and an upper electrode formed over thedielectric layer.
 2. The capacitor of claim 1, wherein the agglomeratescomprise a low-melting-point metal.
 3. The capacitor of claim 2, whereinthe low-melting-point metal comprises at least one of Sn or Zn.
 4. Thecapacitor of claim 1, wherein the dielectric layer comprises at leastone of Si₃N₄, SiO₂, Ta₂O₅, TiO₂, PZT, PLZT, and BaTiO₃.
 5. The capacitorof claim 1, wherein the diffusion barrier comprises Ru.
 6. The capacitorof claim 1, wherein the agglomerates have a spherical shape.
 7. Thecapacitor of claim 1, wherein a projected area of all of theagglomerates constitutes about 50˜60% of an area of the diffusionbarrier.
 8. The capacitor of claim 1, wherein the diffusion barriercomprises RuO₂.
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